1. Technical Field
The present invention relates generally to electrical circuitry and in particular to a method and apparatus for managing timing of electrical signals. Still more particularly, the present invention relates to a method and apparatus for equalizing delays in parallel data transmissions.
2. Description of the Related Art
In many computer systems, small computer system interface (SCSI) buses are used as an architecture for data transfer within a computer. Previous standards for SCSI contain data transfer rates that were slow relative to data propagation skews. Timing budgets for SCSI devices and transfer mediums were generous in these previous standards. These timing budgets were generous in that the normal design and layout techniques taken and device designed, board layout, and cable routing allowed for these timings to be met. With each progressive generation in the SCSI standard, the data skewed became a larger percentage of the transfer. The largest delay in these designs are due to physical transmission lines in parallel SCSI systems. Each of these transmission lines may have different delays in which pulses or signals will arrive at different times in response to the signals being sent simultaneously.
As the data transfer rates increase in the parallel systems, the variation in propagation delays among the different parallel data channels increase. The delays are also referred to as xe2x80x9cskewxe2x80x9d. This variation at some point becomes too large with respect to the data transfer, thus limiting data transfer rates.
In Table 1, set up and hold timings for single transition data transfers are illustrated for different SCSI standards. Table 2 illustrates set up and hold timings for dual transition data transfers for different SCSI standards. All of the times are in nanoseconds in these tables.
In these examples, signal timing skew includes the cable skew and the signal distortion skew in which the signal distortion includes intersymbol interference (ISI) and signal crossing time through the signal detection range. Each of these tables shows the ideal setup and hold timings for a particular type of transfer for a SCSI standard. The tables also illustrate the amount of chip skew, board skew, and signal timing skew. The final resulting setup and hold times are minimal setup and hold times required for proper signaling under the particular SCSI standard.
In the tables, the columns Budget At Chip, Budget At Connector, and Final show the remaining budget from the Total Budget column resulting from the skew shown in the columns Delay at Chip Skew, Board Skew, and Cable Skew. For example Budget At Chip Skew for Fast-10 is 40 in Table 2 and is obtained by subtracting the Delay at Chip Output (10) from the Total Budget (50). The Budget At Connector (38.4) is obtained by subtracting the Board Skew (1.6) from the Budget At Chip (40) for Fast-10.
The comparison of single transition data transfers in Table 1 for Fast-5 SCSI standard with the Fast-40 SCSI standard shows that the total skew allowed for board and cable routing is 10 nanoseconds for Fast-5 SCSI standard and 5 nanoseconds for Fast-40 SCSI standard. However, relative to the respective transfer half periods this skew goes up from 10% for Fast-5 SCSI standard to 20% for Fast-40 SCSI standard. As the transfer rates increase further, the percentage of timing transfer period taken up by the data skew increases. In Table 2, the Fast-80 SCSI standard allocates 30% of the period to skew in the board and cable routing while requiring more data setup and hold for transmitting devices and providing less data setup and hold time for receiving devices. The minimum setup and hold time periods are 4.5 nanoseconds for each in the single transition Fast-40 SCSI standard while in the dual transition Fast-80 SCSI standard, the standard allows only 1.25 nanoseconds for setup and hold time for the period of 12.5 nanoseconds. In the 4.5 nanosecond example, the period of time is 25 nanoseconds.
As a result, these kind of changes limit any faster data transfers. The present invention recognizes that present SCSI technology does not employ delayed equalization among data channels. Methods of delay and equalization are known in fiber channel technology. These methods are based upon external insertion of resistor/inductor/capacitor (RLC) delay elements in each channel or upon equalization of low-to-high and high-to-low internal delays. Fiber channel lends itself to these types of mechanisms because it is a single channel transmission. These types of mechanisms are prohibitive with the presently available SCSI technology for a number of reasons. First, the SCSI transmission media is often changing. Redundant array of inexpensive drives (RAID) change load and delay in response to removal of drives and the addition of new drives. The large number of parallel channels make external channel delay equalization costly because changes in load require a manual readjustment of the delay for each parallel channel. Additionally, SCSI technology does not provide for access to internal nodes for accurate determination of delay skews among data channels.
Therefore, it would be advantageous to have an improved method and apparatus for equalizing delays or to minimize data skew to allow for greater transfer rates in a SCSI system.
The present invention provides a method and apparatus for managing transmission of data signals in a plurality of data lines. Data signals are received on the data lines and a reference signal. On each of the data lines, a delay between the data signal and the reference signal is measured to form a plurality of delay measurements. A set of delay values from the delay measurements is generated. In a preferred embodiment of the present invention, the delay values are selected to equalize the delay in each of the data lines to have the same delay as the data line having the longest delay. The delay values are used to adjust delay in a transmission in each of the plurality of data signals in the data lines. In the preferred embodiment of the present invention, the reference signal is set such that transitions for the data signals are centered to the middle of a pulse for the reference signal.